1. Field of Invention
The present invention relates to a pulse-width control loop (PWCL), and more particularly, to a PWCL for a clock with any pulse-width ratio within a wide range.
2. Related Art
The clock signal plays an important role in the design of an integrated circuit (IC). In general, the amplitude of the clock signal equals the power supply for the system, the frequency thereof must fit the specification of the whole system, and the phase and pulse-width ratio thereof must be adjusted according to the requirements of the circuit. In other words, with respect to the operation of the whole system, the precision of the characteristics of the clock signal is very important, because it may affect the performance of the whole system. Therefore, when the clock signal is distorted, the application system can not function properly. As a result, in circuit design, the error of the characteristics of the clock signal must be controlled within a small, acceptable range, to avoid affecting the performance of the whole system.
At present, most high-speed digital system designs focus on how to restrain the clock signal from the clock skew and the clock jitter. In many electronic devices (such as microprocessors, and memory interfaces), phase locked loops (PLL) and delay locked loops (DLL) are widely adopted to correct the frequency and phase of the signals. Moreover, with regard to the duty cycle of the clock (i.e., the pulse-width ratio), PWCL has been developed to ensure the precision of the output pulse-width ratio.
Referring to FIG. 1, it is a basic architecture of a PWCL, which mainly includes an input control stage 110, a buffer module 120, a charge pump 130, a low pass filter (LPF) 140, and a transconductor 150, which are connected in series to form a loop, so as to adjust the pulse-width ratio of an output clock CKo to a desired ratio according to the received input clock CKi by a feedback mechanism.
As shown in FIG. 1, when the input control stage 110 receives the input clock CKi, the charge pump 130 converts the pulse-width of the input clock CKi into a current value, and the pulse-width ratio is determined by the ratio of charge to discharge. Then, the current is converted into a voltage signal by the LPF 140. The voltage signal is compared by the transconductor 150 to generate a feedback signal Vf and then the feedback signal Vf is fed back the input control stage 110. Big load is driven by the buffer module 120 formed by a cascade of multiple buffers based on feedback signals Vf with different potentials, for regulating the pulse width of the output clock CKo, thereby obtaining the output clock CKo of desired pulse-width ratio. When the pulse width is locked, the feedback signal Vf is a fixed value.
Referring to FIG. 2, a conventional PWCL controls a first charge pump 132 to charge/discharge a capacitor C1 using a ring oscillator 124, so as to generate a reference potential Vref of 50% duty cycle, and controls a second charge pump 134 to charge/discharge a capacitor C2, so as to generate a comparative potential Vc. The comparative potential Vc is compared with the reference potential Vref by the transconductor 150 to feed a feedback signal Vf back the input control stage 110, thereby adjusting the duty cycle of the buffer chain 122. As such, an input clock CKi with a duty cycle lower or larger than 50% can be adjusted by the buffer chain 122 to generate an output clock CKo with a duty cycle of 50%. At this time, the comparative potential Vc is equal to the reference potential Vref, and the loop is locked. The ring oscillator 124 must generate a reference potential of 50% duty cycle. However, it is difficult to implement in practice, and the loop may be unstable if the oscillated signal frequency selected is inappropriate.
Furthermore, another conventional PWCL is a low-voltage PWCL, as shown in FIG. 3. A push-pull charge pump 136 replaces the whole conventional feedback path. In this case, the comparator, i.e., transconductor in the conventional architecture, is not required in the whole circuit, so the circuit is more suitable to operate under a low voltage. However, as the input clock CKi is also used as a basis for generating a reference voltage, the input clock CKi must be a signal with 50% duty cycle. Therefore, the application range of the PWCL is limited.
Furthermore, another conventional PWCL is a complementary PWCL, as shown in FIG. 4, for solving the problem of a requirement of a reference voltage. In this case, a buffer module 120 generates complementary signal, to causing a 180° phase difference between the input clocks of the first charge pump 132 and the second charge pump 134. As the phase difference is generated partially, the variation of the phase difference is not too great. When the loop is not locked, the first comparative potential Vc+ and the second comparative potential Vc− have opposite actions. As compared with the conventional circuit architecture (referring to FIG. 1), the reference potential Vref of the complementary PWCL must be a fixed value, and only the comparative potential Vc thereof can vary. Therefore, in the complementary circuit architecture, the variation of the feedback signals Vf output by the comparator after each comparison is twice of a conventional one, such that it can be locked fast. However, under the circuit architecture, as the ratio of charge to discharge of the charge pump is fixed, only the output clock CKo of 50% duty cycle can be output, such as to limit its application range to some extent.
Referring to FIG. 5, it is another conventional PWCL, which is a fast-Locking PWCL. A voltage-difference-to-digital converter (VDDC) 160 is used to compare the reference potential Vref and the comparative potential Vc, for generating different digital signals to control a switched charge pump 138 to change its current amount at different voltage differences, thereby accelerating the circuit operation to achieve fast locking. Moreover, as the switched charge pump is adopted, when the ratio of charge to discharge of the switched charge pump varies, an output clock CKo with non-50% duty cycle is also generated. However, it is difficult to keep the ratio of charge to discharge during switching the on/off of the charge pump precise, so the range of the output duty cycle only falls in 35%˜70%, and the scale of each adjustment is 5%. Besides, as the design of the VDDC 160 is similar to a flash analog to digital converter (Flash ADC), more power is consumed to achieve fast phase-locking.
Another conventional PWCL is a phase-locking PWCL, as shown in FIG. 6. A synchronous mirror delay (SMD) module 170 is used to control the delay time of the input clock CKi, so as to achieve the phase-locking of the input clock CKi and the output clock CKo. Further, a digital controlled charge pump (DCCP) 139 is used to control different current ratios, so as to output the output clock CKo with non-50% duty cycle. Likewise, the ratio of charge to discharge can not be also kept precise when switching the on/off of the charge pump, so in this circuit architecture, the range of the duty cycle of the output clock just falls in 20% to 50%, wherein the scale of each adjustment is 10%.
In view of the above, though each of the conventional circuit architectures has its own emphasized functions, the acceptable range of the pulse-width ratio (i.e., the duty cycle) of the input/output clock is limited, thus causing problems such as, a complicated architecture, increased power consumption, or large dimensions when fabricating a chip. Besides, some circuit architectures can only output the output clocks with 50% pulse-wide ratio, and a few of circuit architectures which can control the pulse-width ratios of the output clocks have the poor acceptable ranges and resolutions. Therefore, how to generate the output clocks with any pulse-width ratio within a wide range (unlimited, for example, duty cycle 1%˜99%) and/or input the input clocks with any pulse-width ratio within a wide range (unlimited, for example, duty cycle 1%˜99%) becomes a very important in PWCL, thereby providing wider applications.